1. Field of the Invention
The present invention relates to an information processing apparatus, a method of processing information, and a program for processing information and, more specifically, relates to an information processing apparatus, a method of processing information, and a program for processing information that are capable of controlling communication among a plurality of devices via a common communication channel in accordance with priority levels.
2. Description of the Related Art
As methods of bus arbitration, there are known methods of arbitrating access in a fair manner based on a round-robin method or arbitrating the order of access based on a fixed-priority method.
According to the round-robin method, a plurality of masters occupies the buses in sequence, regardless of the processing state. Therefore, unnecessary waiting time is generated, and access of the masters becomes inefficient.
According to the fixed-priority method, if the priority level of a master frequently sending access requests is set high, access requests from other masters having lower priority levels will not be accepted, and the system operation will fail.
FIG. 1 is a block diagram illustrating the structure of a known apparatus employing the fixed-priority method. The apparatus shown in FIG. 1 includes a master A 31, a master B 32, a masters C 33, and a masters D 34 that are connected to a bus arbitrating mechanism (hereinafter referred to as an “arbitrator”) 35.
Among the masters A 31, B 32, C 33, and D 34, the master A 31 has the highest priority level, the master B 32 has the second highest priority level, the masters C 33 has the third highest priority level, and the masters D 34 has the fourth highest priority level.
When the arbitrator 35 receives an access request from the master A 31, B 32, C 33, or D 34, the arbitrator 35 responds to the access request from the master having the highest priority level among all the masters sending access requests and permits access of this master. Either the master A 31, B 32, C 33, or D 34 is permitted access after receiving a response from the arbitrator 35.
For example, when the masters A 31, B 32, C 33, and D 34 simultaneously send access requests, the masters are arbitrated on the basis of their priority levels. Therefore, the request from the master A 31 having the highest priority level is received with priority. In this case, the arbitrator 35 responds to the master A 31, and then the master A 31 is permitted accesses.
Hereinafter, the priority levels are referred to as priority level 1, priority level 2, priority level 3, priority level 4, and priority level 5, where priority level 1 is the highest priority level and priority level 5 is the lowest priority level.
FIG. 2 is a timing chart of a known case in which access requests from and responses to the masters A 31, B 32, C 33, and D 34 when the delay time from sending a request to receiving a response is equal to 1 clock pulse.
The timing chart in FIG. 2 illustrates, from top to bottom, a clock pulse, a request from the master A 31, a request from the master B 32, a request from the master C 33, a request from the master D 34, a response to the master A 31, a response to the master B 32, a response to the master C 33, and a response to the master D 34. Timings T1 to T23 each represent the rising time of clock pulses.
As shown in FIG. 2, when, at the timing T3, access requests are simultaneously sent from the master A 31 and the master B 32, the arbitrator 35 responds to the master A 31, having higher priority, and does not respond to the master B 32. Thus, at the timing T3, the master A 31 is permitted access but the master B 32 is not.
Similarly, when, at the timing T5, access requests are simultaneously sent from the master B 32 and the master C 33, the arbitrator 35 responds to the master B 32, having higher priority, and does not respond to the master C 33. Thus, at the timing T5, the master B 32 is permitted access but the master C 33 is not.
When, at the timing T7, an access request is sent only from the master C 33, the arbitrator 35 responds to the master C 33. Thus, at the timing T7, the master C 33 is permitted accesses. When, at the timing T9, an access request is sent only from the master D 34, the arbitrator 35 responds to the master D 34, and the master D 34 having the lowest priority level is permitted access.
Since, between timings T12 and 16, access requests are simultaneously sent from the masters A 31, B 32, C 33, and D 34, the master A 31 having the highest priority level is permitted exclusive accesses. With the priority levels fixed, if a access request from the master A 31 extends for a long period of time, as shown in FIG. 2, access requests from the masters B 32, C 33, and D 34 whose priority levels are lower than that of the master A 31 are completely rejected. Therefore, the priority levels of the masters must be determined carefully based on the order of priority of processing.
Accordingly, a mechanism for changing the access order is commonly provided. For example, a method that allows fine control of the priority levels by controlling the time intervals of access requests on the master side using a simply bus arbitration mechanism is known (for example, refer to Japanese Unexamined Patent Application Publication No. 2003-186824).